A block diagram of a typical direct sequence spread spectrum system 100 is shown in FIG. 1. A transmitter 102 consists of an MPSK modulator 104 which typically utilizes either Binary (BPSK) or Quaternary (QPSK) phase shift keying, followed by a spreader 106 which multiplies the modulated signal by a digital PN (pseudo noise) spreading code 108. The PN code 108 is typically generated by a PN Code Generator 110 at a rate (referred to as the chipping rate) at least an order of magnitude faster than a data symbol rate of the modulator 104, thus spreading the spectrum across a much greater bandwidth. For a multiple user system, each user has his own unique PN code and the bandwidth can be shared among different users using code division multiple access (CDMA) techniques.
A receiver 112 generates an exact replica 109 of the transmit PN sequence and multiplies it by the received signal to despread and hence recover the original modulated waveform. The receiver 112 must incorporate some means of synchronizing the timing of the locally generated PN sequence to that of the received signal. Both code acquisition circuitry 111 and tracking circuitry 113 must be included.
The receiver 112 structure typically uses one of three general structures as shown in FIGS. 2(a), (b) and (c). In FIG. 2(a), the receiver RF input 200 is first downconverted to a wideband intermediate IF frequency signal 214 in a wideband IF stage 208. The IF bandwidth must be greater than the spread bandwidth of the transmit signal. The IF signal 214 is then despread by a PN sequence 204 which has been upconverted from baseband to the IF frequency. The resulting despread signal 206 appears at baseband and is then filtered by a narrowband lowpass filter 202 with a bandwidth on the order of the data symbol rate.
A second scheme, shown in FIG. 2(b), also downconverts the RF signal 200 in the wideband IF stage 208. The despreading operation occurs at the IF frequency, although it is accomplished by multiplying the IF signal 214 by the baseband PN sequence 215. After despreading, the signal bandwidth is reduced, and the signal can then be filtered with a narrowband IF filter 210. The narrowband signal is then downconverted to baseband in the narrowband IF stage followed by narrowband baseband filtering.
The third scheme performs despreading at baseband as shown in FIG. 2(c). The wideband RF signal 200 is downconverted to a wideband baseband signal 216 and then filtered with a wideband baseband filter 212. The baseband signal is then despread by multiplying it by the baseband PN sequence 215 followed by narrowband baseband filtering.
One disadvantage of an all analog implementation of the IF and despreading circuits is the large number of components typically required. Each IF stage requires a local oscillator, mixer and filter. The despreading mixer must remain flat over a large bandwidth and accept a high slew-rate digital PN input. If pre-filtering is employed prior to despreading to improve noise performance, it typically exhibits a non-ideal frequency and time delay response, resulting in sub-optimum performance. The narrowband filter following the despreader should be reasonably sharp, often resulting in a physically large device. The baseband version of the despreader requires a complex downconverter where the local oscillator must be split into its in-phase and quadrature components. In addition, the phase noise of the local oscillators must be tightly controlled or there will be a performance loss in the subsequent coherent MPSK demodulator. DC offsets are also a concern and should be removed prior to demodulation. Analog circuits also suffer from component drift and aging and may be difficult to obtain with very tight tolerances.
Although the PN sequence is generated using digital techniques, the remaining circuitry has often been implemented using analog techniques. The digitally modulated MPSK signal is typically not converted to digital form until after the despreading operation. However, recently there has been great interest in implementing the despreader in digital form as well. A block diagram of a prior art digital despreader 300 which performs despreading at baseband is shown in FIG. 3. The scheme accepts a wideband IF signal 214 as depicted in FIG. 2(c) and digitally samples it directly in the wideband IF stage using A/D converter 301. After sampling by the A/D converter 301, the signal 308 is downconverted to baseband by digitally multiplying it by in-phase 310 and quadrature 312 numerically controlled oscillators. The complex baseband signal is filtered with a very broad accumulate and dump filter 304 which simply averages two adjacent samples. The filtered signal is then despread with a baseband PN sequence. The steerable clock generator 302, which is controlled by an external chip timing control signal 306, outputs a sample clock 314 to the A/D converter 301. The timing phase must be accurately controlled according to the PN timing acquisition 111 and tracking 113 mechanisms following the despreader.
The prior art digitally implemented downconverter/despreader has overcome many of the disadvantages of equivalent analog circuits. Only a single A/D converter is required and sampling is performed directly in the wideband IF where DC offsets can easily be removed. However, this scheme still requires a sampling rate approximately an order of magnitude higher than the chipping rate due to the poor amplitude response of the baseband digital filter 304 following the downconverter. A disadvantage inherent to all of the prior art methods is that they each use an analog clock circuit to track the timing phase of the PN sequence. Such a circuit must be highly stable and shielded from external noise sources. It also requires a finite amount of settling timing to slew the clock to a desired timing phase value and suffers from phase jitter about the nominal value. In addition, the circuitry needed to precisely adjust the phase of the high frequency chip timing clock is often complex. Recent digital implementations of the steerable clock generator 302 utilize direct digital synthesis where a numerically controlled oscillator drives a high frequency D/A converter. This is an expensive solution.
The digital scheme as shown in FIG. 3 has a second problem with timing control. Timing synchronization is accomplished by adjusting the phase of the A/D converter sample clock prior to the downconversion operation. The IF sub-sampling technique employed actually creates an alias of the IF signal separated from the IF frequency by an integral multiple of the sample rate, f.sub.s. However, as the sample rate is changed by the clock generator circuitry to track the PN timing, the carrier frequency and phase change by a multiple of f.sub.s. This can cause excessive phase jitter in the carrier phase and requires some means of compensation.
There are many examples found in the prior art which attempt to correct the above-noted shortcomings. Cowart, in related U.S. Pat. Nos. 5,029,180, 5,189,683 and 5,146,471, represents a low-cost implementation of a direct sequence spread spectrum (hereafter referred to as DS SS) transceiver suitable for integration into a single chip. Cowart assumes that the carrier frequency, chip rate, and data symbol rate are all synchronized from a common frequency source. Cowart also requires that the actual receive frequency and the receiver reference oscillator frequency be nearly identical by deriving them from stable crystal oscillators at frequencies below 50 MHZ. The primary application of Cowart is for transmission over power lines.
Cowart, however, uses hard-limiting in the receiver and only performs coarse timing tracking (within +/-1/4 of a chip period) of the received PN (pseudo noise) chipping sequence. In addition, Cowart cannot make precise chip timing adjustments and the bit error performance over noisy channels is sub-optimal.
Omura et al., in U.S. Pat. Nos. 5,166,952, 5,157,686 and 5,253,268, discuss a DS SS receiver and transmitter which employ either pulse position modulation or multiple chip code modulation. A matched filter correlator, matched to the transmit PN codes, is described followed by non-coherent demodulation.
Although the receiver of Omura performs digital sampling of the signal prior to despreading at a sample rate which is an integral multiple of the PN chip rate, two A/D converters are required. In addition, downconversion is performed by analog means and there is no fine tracking of the received PN chip timing. The resolution of chip timing adjustments is a function of the A/D sample rate and thus an excessively high sample rate is required for high resolution adjustment. In this solution, the bit error performance over noisy channels is also sub-optimal.
Soleimani, et al., U.S. Pat. No. 5,208,829, disclose a satellite communications system for providing maximum power output in a spread spectrum signal transmission. Filter designs for both the transmitter and receiver which provide a maximally flat frequency response over the band of interest are given. A receiver structure is described which can receive either spread or non-spread signals.
The spread-spectrum receiver design of Soleimani is based on conventional techniques. The receiver performs A/D conversion prior to despreading, but two converters are required rather than one. The receiver structure performs analog downconversion to baseband prior to despreading and the PN chip timing adjustments require an external VCXO circuit. This solution requires a high number of precision components making it expensive and complex.